1 ? synchronous rectified mosfet driver the ISL6605 is a high frequency, mosfet driver optimized to drive two n-channel power mosfets in a synchronous- rectified buck converter topology. this driver combined with an intersil hip63xx or isl65xx multi-phase buck pwm controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for ad vanced microprocessors. the ic is biased by a single low voltage supply (5v) and minimizes low driver switching losses for high mosfet gate capacitance and high switchin g frequency applications. each driver is capable of dr iving a 3000pf load with a 8ns propagation delay and less than 10ns transition time. this product implements bootstrappi ng on the upper gate with an internal bootstrap schottky di ode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective n-channel mosfets. adaptive shoot-through protection is integrated to prevent both mosfets from conducting simultaneously. the ISL6605 features 4a typical sink current for the lower gate driver, which is capable of holding the lower mosfet gate during the phase node risi ng edge to prevent shoot- through power loss caused by the high dv/dt of the phase node. the ISL6605 also features a three-state pwm input that, working together with intersil multi-phase pwm controllers, will prevent a negative transi ent on the output voltage when the output is being shut down. this feature eliminates the schottky diode that is usually seen in a microprocessor power system for protecting the microprocessor from reversed-output-voltage damage. features ? drives two n-channel mosfets ? adaptive shoot-through protection ?0.4 ? on-resistance and 4a sink current capability ? supports high switching frequency - fast output rise time - propagation delay 8ns ? three-state pwm input for power stage shutdown ? internal bootstrap schottky diode ? low bias supply current (5v, 30 a) ? enable input ? qfn package - compliant to jedec pub95 mo-220 qfn-quad flat no leads-product outline. - near chip-scale package footprint; improves pcb efficiency and thinner in profile. applications ? core voltage supplies for intel? and amd? microprocessors ? high frequency low profile dc-dc converters ? high current low voltage dc-dc converters ? synchronous rectification for isolated power supplies related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? pinouts ordering information part number temp. range ( o c) package pkg. no. ISL6605cb 0 to 70 8 ld soic m8.15 ISL6605cb-t 8 ld soic tape and reel ISL6605cr 0 to 70 8 ld 3x3 qfn l8.3x3 ISL6605cr-t 8 ld qfn tape and reel ISL6605ib -40 to 85 8 ld soic m8.15 ISL6605ib-t 8 ld soic tape and reel ISL6605ir -40 to 85 8 ld 3x3 qfn l8.3x3 ISL6605ir-t 8 ld qfn tape and reel isl6558eval2 evaluation platform (isl6558ir+ISL6605ir) ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase en vcc lgate boot gnd lgate ugate en vcc 1 2 3 5 7 8 4 6 pwm phase ISL6605 8 lead (soic) top view ISL6605 8 lead (qfn) top view fn9091.2 ISL6605 data sheet august 2003 caution: these devices are sensitive to electros tatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 ti typical application - multi-phase c onverter using ISL6605 gate drivers block diagram ISL6605 vcc pwm vcc 20k 20k control logic shoot- through protection boot ugate phase lgate gnd vcc en +5v boot ugate phase lgate pwm en vcc v in +5v boot ugate phase lgate pwm v in +v core pgood vid fs/en gnd isen2 isen1 pwm2 pwm1 vsen pwm fb vcc +5v comp ISL6605 control vcc ISL6605 +5v en (hip63xx (optional) or isl65xx) 499k* 499k* * 499k is used to pull down the pwm input to preven t the pwm from false triggering ugate during startup. ISL6605
3 absolute maximum rati ngs thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v boot voltage (v boot ). . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 22v phase voltage (v phase ) . . . . . . . . . v boot - 7v to v boot + 0.3v input voltage (v en , v pwm ) . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v ugate. . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v ambient temperature range. . . . . . . . . . . . . . . . . . -40 o c to 125 o c esd rating human body model . . . . . . . . . . . . . . . . . . . class 1 jedec std recommended operating conditions ambient temperature range. . . . . . . . . . . . . . . . . . -400 o c to 85 o c maximum operating junction temperatur e. . . . . . . . . . . . . . 125 o c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% thermal resistance (notes 1, 2, 3) ja ( o c/w) jc ( o c/w) soic package (note 1) . . . . . . . . . . . . 110 n/a qfn package (notes 2, 3). . . . . . . . . . 95 36 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. 3. jc , "case temperature" location is at the center of the package underside exposed pad. see tech brief tb379 for details. electrical specifications these specifications apply for t a = -40 c to 85 c, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc en = low - - 5.0 a bias supply current i vcc pwm pin floating, v vcc = 5v - 30 - a pwm input input current i pwm v pwm = 5v - 250 - a v pwm = 0v - -250 - a pwm three-state rising threshold v vcc = 5v, t a = 0 c to 70 c--1.70v v vcc = 5v, t a = -40 c to 85 c--1.75v pwm three-state falling threshold v vcc = 5v 3.3 - - v three-state shutdown holdoff time v vcc = 5v, temperature = 25 c - 420 - ns en input en low threshold 1.0 - - v en high threshold --2.0v switching time ugate rise time t rugate v vcc = 5v, 3nf load - 8 - ns lgate rise time t rlgate v vcc = 5v, 3nf load - 8 - ns ugate fall time t fugate v vcc = 5v, 3nf load - 8 - ns lgate fall time t flgate v vcc = 5v, 3nf load - 4 - ns ugate turn-off propagation delay t pdlugate v vcc = 5v, 3nf load - 8 - ns lgate turn-off propagation delay t pdllgate v vcc = 5v, 3nf load - 8 - ns output upper drive source resistance r ugate 500ma source current - 1.0 2.5 ? upper driver source current (note 4) i ugate v ugate-phase = 2.5v 2.0 a upper drive sink resistance r ugate 500ma sink current - 1.0 2.5 ? upper driver sink current (note 4) i ugate v ugate-phase = 2.5v 2.0 a lower drive source resistance r lgate 500ma source current 1.0 2.5 ? lower driver source current (note 4) i lgate v lgate = 2.5v 2.0 a lower drive sink resistance r lgate 500ma sink current - 0.4 1.0 ? lower driver sink current (note 4) i lgate v lgate = 2.5v 4.0 a note: 4. guaranteed by design. not 100% tested in production. ISL6605
4 functional pin description note: pin numbers refer to the soic package. check pinout diagrams for qfn pin numbers. ugate (pin 1) upper gate drive output. connec t to gate of high-side power n-channel mosfet. boot (pin 2) floating bootstrap supply pin for the upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capaci tor provides the charge to turn on the upper mosfet. see the bootstrap diode and capacitor section under description for guidance in choosing the appropriate capacitor value. pwm (pin 3) the pwm signal is the control input for the driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to th e pwm output of the controller. gnd (pin 4) ground pin. all signals are referenced to this node. lgate (pin 5) lower gate drive output. conne ct to gate of the low-side power n-channel mosfet. vcc (pin 6) connect this pin to a +5v bias supply. place a high quality bypass capacitor from this pin to gnd. en (pin 7) enable input pin. connect this pin to high to enable and low to disable the ic. when disabled, the ic draws less than 1 a bias current. phase (pin 8) connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate driver. thermal pad (in qfn only) in the qfn package, the pad underneath the center of the ic is a thermal substrate. the pcb ?thermal land? design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). this combination of vias for vertical heat escape and buried planes for heat spreading allows the qfn to achieve its full thermal potential. this pad should be either grounded or floating, and it should not be connected to other nodes. refer to tb389 for design guidelines. description operation designed for speed, the ISL6605 mo sfet driver controls both high-side and low-side n-channel fets from one externally provided pwm signal. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram). after a short propagation delay [t pdllgate ], the lower gate begins to fall. typical fall times [t flgate ] are provided in the electrical specifications section. adaptive shoot-through circuitry monitors the lgate voltage and determines the upper gate delay time [t pdhugate ] based on how quickly the lgate voltage drops below 1v. this prevents both the lower and upper mosfets from conducting simultaneously or shoot- through. once this delay period is completed the upper gate drive begins to rise [t rugate ] and the upper mosfet turns on. a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlugate ] is encountered before the upper gate begins to fall [t fugate ]. again, the adaptive shoot-through circuitry determines the lower gate delay time, t pdhlgate . the upper mosfet gate voltage is monitored and the lower gate is allowed to rise after the upper mosfet gate-to-source voltage drops below 1v. the lower gate then rises [t rlgate ], turning on the lower mosfet. timing diagram pwm ugate lgate t pdllgate t flgate t pdhugate t rugate t pdlugate t fugate t pdhlgate t rlgate ISL6605
5 this driver is optimized for vo ltage regulators with large step down ratio. the lower mosfet is usually sized much larger compared to the upper mosfet because the lower mosfet conducts for a much longer time in a switching period. the lower gate driver is therefore sized much larger to meet this applicatio n requirement. the 0.4 ? on-resistance and 4a sink current capability enable the lower gate driver to absorb the current injected to the lower gate through the drain-to-gate capacitor of th e lower mosfet and prevent a shoot through caused by the hi gh dv/dt of the phase node. three-state pwm input a unique feature of the ISL6605 and other intersil drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in th e electrical specifications determine when the lower and upper gates are enabled. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 1v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the upper mosfet gate voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. internal bootstrap diode this driver features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the boots trap circuit.the bootstrap capacitor can be chosen from the following equation: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. the above relationship is illustrated in figure 1. as an example, suppose an upper mosfet has a gate charge, q gate , of 65nc at 5v and also assume the droop in the drive voltage over a pw m cycle is 200mv. one will find that a bootstrap capacitance of at least 0.125 f is required. the next larger standard value capacitance is 0.22 f. a good quality ceramic capacitor is recommended. power dissipation package power dissipation is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125 o c. the maximum allowable ic power dissipation for the so-8 package is approximately 800mw. when de signing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the driver is approximated as below and plotted as in figure 2. where f sw is the switching frequency of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l are the upper and lower gate charge determined by mosfet selection and any external capacitance added to the gate pins. the i ddq v cc product is the quiescent power of the driver and is typically negligible. c boot q gate ? v boot ----------------------- - ? v boot (v) c boot (uf) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1. 0 q gate = 100 nc 50nc 20nc 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 50nc 20nc q gate =100nc figure 1. bootstrap capa citance vs. boot ripple voltage pf sw 1.5v u q u v l q l + () i ddq v cc + = ISL6605
6 application information fault mode at repetitive startups at a low vcc (<2v), the thevenin equivalent of the 20k divider at the pwm pin, as shown in the block diagram on page 2, is no longer true; ve ry high impedance will be seen from the pwm pin to gnd. junction leakage currents from the vcc to the resistor tub will tend to pull up the pwm input and falsely trigger the ugate. if the energy stored in the bootstrap capacitor is not completely discharged during the previous power-down period, then the upper mosfet could be turned on and generate a sp ike at the output when vcc ramps up. a 499k ? resistor at the pwm to gnd, as shown in figure 3, helps bleed the leakage currents, thus eliminating the startup spike. layout considerations and mosfet selection the parasitic inductances of the pcb and the power devices (both upper and lower fets) generate a negative ringing at the trailing edge of the phase node. this negative ringing plus the vcc adds charges to the bootstrap capacitor through the internal bootst rap schottky diode when the phase node is low. if the negative spikes are too large, especially at high current applications with a poor layout, the voltage on the bootstrap capac itor could exceed the vcc and the device?s maximum rating. the v boot-phase voltage should be checked at the worst case (maximum vcc and prior to overcurrent load), especially for applications with higher than 20a per d 2 pak fet. mosfets with low parasitic lead inductances, such as multi-source leads devices (so-8 and lfpak), are recommended. careful layout would help reduce the negative ringing peak significantly: - tie the source of the u pper fet and the drain of the lower fet as close as possible; - use the shortest low-im pedance trace between the source of the lower fet and the power ground; - tie the gnd of the ISL6605 closely to the source of the lower fet. furthermore, placin g a resistor (r boot ) across the boot and phase pins can help reduce couple tenth of volts on the bootstrap capacitor when necessary. however, this will require a relatively low load impedance; if not, the divider formed by the r boot and the load impedance would generate some output voltage at the shutdown mode with the vcc remaining high. the r boot also helps discharge the bootstrap capacitor and eliminate the startup spike discussed in previous section if the repetitive startup rate is relative low. having a smt0 805 resistor placement for the r boot in the design is recommended as shown in figure 5; it will come handy when needed. when placing the qfn part on the board, no vias or trace should be running in between pin numbers 1 and 8 since a small piece of copper is underneath the corner for the orientation. in addition, con necting the thermal pad of the qfn part to the power ground wit h a via, or placing a low noise copper plane underneath the soic part is strongly recommended for high switching frequency, high current applications. this is for heat spreading and allows the part to achieve its full thermal potential. 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 q u =50nc q l =50nc q u =50nc q l =100nc q u =100nc q l =200nc q u =20nc q l =50nc power (m ? ) figure 2. power dissipation vs. frequency pwm ISL6605 499k gnd figure 3. 499k ? resistor phase negative spike figure 4. typical phase node voltage waveform ISL6605 (do not populate) boot phase c boot r boot figure 5. smt0805 resistor placement for the r boot ISL6605
7 ISL6605 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l8.3x3 8 lead quad flat no-lead plastic package (compliant to jedec mo-220veec issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 0.25 1.10 1.25 7, 8 e 3.00 bsc - e1 2.75 bsc 9 e2 0.25 1.10 1.25 7, 8 e 0.65 bsc - k0.25 - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n82 nd 2 3 ne 2 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6605 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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